46 avenue Felix Viallet
Grenoble,  F-38031

  • Booth: 813

CMP is a service organization in ICs and MEMS for prototyping and low volume productions.

  • CMP provides several regular and advanced CMOS technologies. BiCMOS RF, High voltage and Smart power are among our Specialty technology portfolio.
  • CMP provides two types of MEMS technologies for prototyping: Integrated bulk micromachining technologies and specific surface micromachining technologies

Since 1981, more than 1000 Institutions from 70 countries have been served, more than 6700 projects have been prototyped through 800 runs, and 60 different technologies have been interfaced.

 Press Releases

  • GRENOBLE, France – 11 July, 2016 – IRT Nanoelec, an R&D consortium focused on information and communication technologies (ICT) using micro and nanoelectronics, and CMP, Circuits Multi-Projets®, a service organization in ICs and MEMS prototyping and low volume production, today announced the IC industry’s first multi-project wafer (MPW) process for fabricating silicon-photonics devices on a 310nm silicon on insulator (SOI) platform. The MPW service also includes compatible IC MPW services and the first service for post-process 3D integration on multi-project wafers. IRT, which is headed by CEA-Leti, and CMP announced that service in 2015.

    Available on Leti’s 200mm CMOS line, the MPW service provides a comprehensive, very low-cost way to address the challenges of achieving miniaturization and high-density components. An electronic chip can be flip chip assembled on top of the photonics chip.

    “Fabricating photonics technology on silicon is complex and costly, which has been an entry barrier for many research organizations and fabless companies,” said Maryse Fournier, IRT MPW Project Manager. “This MPW capability on a 310nm SOI platform provides drastic cost-saving advantages, and opens the door for them to create products for long-haul telecom, short-reach datacom, optical switching in datacenters and other markets that require the speed and capacity that silicon photonics offers.” This technology offer comes with a Design Kit, including layout, verification and simulation capabilities. Libraries are provided with comprehensive list of active and passive electro-optical components. The design kit environment is compatible with full 3D integration offers through CMP.

    “This Silicon Photonics 310nm on SOI, multi-project wafer capability along with complementary 3D post-process services bring our IC community another step closer to a complete process, which includes through-silicon-via last, fine-pitch vertical interconnects and specific finishing for 3D integration like under-bump metallization,” said Jean-Christophe Crébier, Director of CMP . “It also can significantly speed the development of new silicon-photonics devices that meet constantly growing data-handling requirements.”

    About IRT-Nanoelec Research Technological Institute (IRT)

    Nanoelec Research Technological Institute (IRT), headed by CEA-Leti conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics. Based in Grenoble, France, IRT Nanoelec leverages the area’s proven innovation ecosystem to create the technologies that will power the nanoelectronics of tomorrow, drive new product development and inspire new applications – like the Internet of Things – for existing technologies. The R&D conducted at IRT Nanoelec provides early insight into how emerging technologies such as 3D integration and silicon photonics will affect integrated circuits. Visit IRT Nanoelec is partly funded by the French “Programme d’Investissements d’Avenir”

    About CMP

    CMP is a service organization in ICs and MEMS for prototyping and low volume production. CMP enables prototypes fabrication on industrial processes at very attractive costs and offers it great technical expertise in providing MPW and related services for Universities, Research Laboratories and Industrial companies’ prototyping. Chips are normally untested and delivered packaged or not. Advanced industrial technologies are made available in CMOS, SiGe BiCMOS, HV-CMOS, SOI, MEMS, 3D-IC, etc. Since 1981 more than 1000 Institutions from 70 countries have been served, more than 7000 projects have been prototyped through a thousand runs, and 71 different technologies have been interfaced. For more information, visit:

  • Geneva, Switzerland, and Grenoble, France, 21 January 2015 — STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, and CMP (Circuits Multi Projets®) have made ST’s BCD8sP technology platform for smart-power ICs available for prototyping to universities, research labs, and design companies through the silicon brokerage services provided by CMP.

    This is the first time ST has released BCD design capability to third parties, which reflects the growing importance of state-of-the-art power integration in the drive for higher performance in computing, consumer, and industrial applications of the future. “We expect CMP to help us identify and support innovative projects, and hopefully establish long-term connections with talented designers and research organizations,” said Claudio Diazzi, Sense & Power and Automotive Sector, Front End Manufacturing and Technology R&D, VP-Smart Power Technologies in STMicroelectronics.

    The most advanced of ST’s Bipolar-CMOS-DMOS (BCD) technologies in production, the BCD8sP process enables the integration of analog and logic circuitry with high-voltage power components to produce single-chip devices for complex power-conversion and control applications. The process has enabled ST to leapfrog its competitors in important smart-power applications such as Hard Disk Drive (HDD) controllers, motor controllers, and power-management ICs for equipment such as smartphones, tablets, and computer servers.

    The introduction in CMP’s catalog of ST’s BCD8sP process builds on the successful collaboration that has allowed universities and design firms to access leading-edge and previous bulk CMOS generations including 28nm, 65nm, and 130nm. CMP’s clients also have access to 28nm FD-SOI and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics.

    “With ST’s world-class BCD process in our portfolio, we can now provide even stronger support for advanced smart-power design projects,” said Jean-Christophe Crebier, Director of CMP. “Many top universities worldwide have already taken advantage of the collaboration between CMP and ST. About 300 projects have been designed in ST’s 90nm process, more than 350 in bulk 65nm, and already over 50 projects prototyped in 28nm FD-SOI.”

    About STMicroelectronics

    ST is a global leader in the semiconductor market serving customers across the spectrum of sense and power and automotive products and embedded processing solutions. From energy management and savings to trust and data security, from healthcare and wellness to smart consumer devices, in the home, car and office, at work and at play, ST is found everywhere microelectronics make a positive and innovative contribution to people's life. By getting more from technology to get more from life, ST stands for life.augmented.

    In 2013, the Company’s net revenues were $8.08 billion. Further information on ST can be found at

    About CMP

    CMP is a service organization in ICs and MEMS for prototyping and low volume production. Circuits are fabricated for Universities, Research Laboratories and Industrial companies.

    Advanced industrial technologies are available in CMOS, SiGe BiCMOS, HV-CMOS, SOI, P-HEMT GaAs, MEMS, 3D-IC, etc. CMP distributes and supports several CAD software tools for both Industrial Companies and Universities.
    Since 1981, more than 1000 Institutions from 70 countries have been served, more than 6700 projects have been prototyped through 800 runs, and 60 different technologies have been interfaced. For more information, visit:
  • New platform provides access to 3D technologies after regular CMOS MPW runs and allows SMEs, research institutes, systems integrators and universities to divide costs

    GRENOBLE, France – March 5th, 2015 – IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

    The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

    This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

    3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEM, and involves wafer-level processing on dedicated runs.


    The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

    These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

    More information about this 3D-MPW offer and the 3D technologies from IRT Nanoelec and CMP is available on the websites and

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