Scaling: Node 10 to Node 5 - Dealing with the Slower Pace of Traditional Scaling

  • Location:North Hall, Room 133
Tuesday, July 12, 2016: 2:00 PM - 4:00 PM

Speaker(s)

Speaker
Guy Blalock
Vice President of Central Operations
Micron Technology
Speaker
Mike Chudzik Ph.D.
Sr. Director of Technical Projects, Transistor and Interconnect Group
Applied Materials
Speaker
David Dutton
CEO
Silvaco
Speaker
Kevin Heidrich
Sr. Vice President, Applications and Strategy
Nanometrics Inc.
Speaker
Lode Lauwers Ph.D.
Vice President, Business Development & Sales
IMEC
Speaker
Kelvin Low
Sr. Director of Marketing, Foundry Services
Samsung Semiconductor
Moderator
Debra Vogler
President & Founder
Instant Insight Inc.

Description

The pace of scaling has been thrown a bit off its “usual” schedule in the last few years, and there is hope that advances in 3D ICs and novel packaging technologies will help ease the industry’s anxieties about the reduced pace and increasing costs. That said, to enable greater functionality in ever more portable platforms, the industry needs to keep scaling alive for as long as possible. This session covers the challenges and potential solutions as the industry strives to get to node 5. Covered topics include materials and process R&D challenges (to get to node 5) as well as alternatives to transistor structures (e.g., nanowires, TFETs).   

Registration 

 
  By June 3 Starting June 4

SEMI Member

$125

$175

Non Member

$175

$225

  


Track


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Presentations:
  • Location:North Hall, Room 133
  • Tuesday, July 12, 2:00 PM - 2:20 PM
    • Location:North Hall, Room 133
    • Tuesday, July 12, 2:20 PM - 2:40 PM
    • Advanced Manufacturing Forum
    • Location:North Hall, Room 133
    • Tuesday, July 12, 2:40 PM - 3:00 PM
      • Location:North Hall, Room 133
      • Tuesday, July 12, 3:00 PM - 3:20 PM
      • Advanced Manufacturing Forum
      • Location:North Hall, Room 133
      • Tuesday, July 12, 3:20 PM - 3:40 PM
        • Location:North Hall, Room 133
        • Tuesday, July 12, 3:40 PM - 4:00 PM