Coventor, Inc.

1000 CentreGreen Way
Cary,  NC  27513

United States
http://www.coventor.com
  • Booth: 2622


See you at Semicon WEST! Visit Coventor in Booth# 2622!

Coventor, Inc. is the market leader in automated design solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley, Waltham, Massachusetts, and Paris, France. More information is available at http://www.coventor.com.


 Press Releases

  • Coventor’s Virtual Fabrication Platform Addresses Increasingly Complex Semiconductor Process Design Challenges

    CARY, NC– June 6, 2016 – Coventor®, Inc., the leading supplier of automated software solutions for semiconductor devices and micro-electromechanical systems (MEMS), today announced the availability of SEMulator3D® 6.0 – the latest version of its semiconductor virtual fabrication platform. This new version further increases the accuracy of the process simulation, geometry and modeling of advanced semiconductor processes with new features, usability enhancements and a new add-on capability for electrical analysis. Along with SEMulator3D 6.0, Coventor is releasing an all-new SEMulator3D Electrical Analysis add-on component that allows seamless resistance and capacitance extraction directly from SEMulator3D process-predictive 3D models.

    SEMulator3D Electrical Analysis

    In semiconductor device fabrication, the various processing steps have grown increasingly complex as smaller semiconductor feature sizes and nodes are developed.   With shrinking process technologies, parasitic effects of devices and interconnects have a significant impact on circuit performance.  SEMulator3D Electrical Analysis builds in new features and solvers so that users can better understand resistance and capacitance impacts of design and process variation.

    “The real break-through here is our ability to solve for resistance and capacitance dramatically faster than any other software, without ever leaving the SEMulator3D environment.  There is no meshing or data export required,” said David Fried, CTO – Semiconductor for Coventor.  “Now, our users can link the process variations in the fab and the design choices of the product to real electrical impact, through process-predictive structural modeling and our new advanced Electrical Analysis tool.”

    SEMulator3D 6.0 Productivity Enhancements

    SEMulator3D 6.0 enables accurate modeling and performance prediction for next-generation processes including FinFETs, 3D NAND Flash, BEOL, Nanowires, 3D-IC, FDSOI, and DRAM.  The new version includes the following usability enhancements:

    • New Analysis Editor environment
      • The tool now separates analysis steps, such as metrology, structure search and parasitic extraction from the process sequence for improved usability, faster analysis run-times and simpler collaborative deployment.
    • Tracking virtual defects
      • Defect insertion and placement has been enhanced to allow for random, systematic and arrayed defectivity, reflecting the various sources of possible manufacturing issues in the fab. This diagnostic improvement enables a known defect to be traced back to the originating process step or tool that may have created it.
    • Support for additional structural export formats
      • SEMulator3D now allows users to export meshes to additional file formats, including dopant concentrations, for use in 3rd-party FEA/BEA software.  This provides users the benefit of having the accuracy of the SEMulator3D process simulation and geometry along with the ability to model additional complex physical phenomena using other tools.

     

    About Coventor

    Coventor, Inc. is the market leader in automated design solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley; Waltham, Massachusetts; and Paris, France.  More information is available athttp://www.coventor.com.

    —end—

    Coventor and SEMulator3D are registered trademarks of Coventor, Inc.  All other trademarks are the property of their respective owners

  • • Joint development team leverages SEMulator3D to explore semiconductor process  variation issues at unprecedented levels
    • Collaboration team has conducted a massive computer modeling simulation of a million
    wafers to explore process variability in 7nm BEOL semiconductor fabrication
    • The extending collaboration aims to further advance the availability, yield and cost of
    manufacturing processes for the next generation of 7 nm semiconductor products

    Leuven, Belgium & Cary, North Carolina, United States – December 7, 2015 – Imec, a
    world-leading nanoelectronics research center and Coventor, a leading supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology.

    For over a year, the joint team has been using Coventor’s semiconductor process modeling platform, SEMulator3D®, to perform predictive modeling of semiconductor fabrication processes and to proactively analyze process variation issues in 7nm semiconductor technology.   The collaboration has now been expanded beyond logic-only devices to include 3D NAND Flash, STT-MRAM, and other device types.

    “Leveraging Coventor’s technical expertise and its SEMulator3D platform has enabled us to solve real-world semiconductor integration and processing problems at the 7nm node,” said An Steegen, senior vice president of process technology at imec. “Our joint collaboration is helping the entire semiconductor industry lower the risks associated with moving to the latest process technologies by providing customers with proven, tested process development platforms and advancing the availability, yield and cost of next-generation semiconductor technology.”

    A highlight of the collaboration has been a massive process simulation experiment to explore the effect of process variability in 7nm BEOL (back end of line) fabrication processes. Researchers used SEMulator3D to simulate an entire window of process variability, which would have required more than one million actual semiconductor wafers if conventional testing methods were used. This experiment was made possible by the robust virtual fabrication environment of SEMulator3D using a fully codified 7nm process flow, along with the ability to support parallel distributed computing and a novel algorithm for submitting variation cases to the simulator.  With these powerful tools, the team was able to produce key findings that will help advance 7nm semiconductor technology.

    “We have worked with imec to accelerate the state of the art in semiconductor process
    technology useful in a broad range of next-generation devices such as Logic, 3D NAND Flash, STT-MRAM, and others,” said David Fried, Chief Technical Officer at Coventor. “By providing our customers with a comprehensive virtual fabrication environment, plus our combined expertise, Coventor and imec are reducing the time and cost associated with moving to these emerging semiconductor nodes.”

    About SEMulator3D
    The SEMulator3D® platform is an integrated set of modeling tools to interactively simulate a wide range of semiconductor processes, and subsequently avoid time-consuming and expensive silicon fabrication and testing. The latest release of the SEMulator3D® platform (Version 5.1) includes many new features, including new process capabilities like DSA process modeling, new automation features such as edge placement error metrology, support for distributed computing clusters and expanded layout capabilities.

    About imec
    Imec performs world-leading research in nanoelectronics. Imec leverages its scientific
    knowledge with the innovative power of its global partnerships in ICT, healthcare and energy.  Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, USA, China, India and Japan. Its staff of about 2,300 people includes almost 700 industrial residents and guest researchers. In 2014, imec’s revenue (P&L) totaled 363 million euro. Further information on imec can be found at www.imec.be. Stay up to date about what’s happening at imec with the monthly imec magazine, available for tablets and smartphones (as an app for iOS and Android), or via the website www.imec.be/imecmagazine.

    About Coventor
    Coventor, Inc. is the market leader in advanced solutions for developing semiconductor process technology, as well as micro-electromechanical systems (MEMS). Coventor serves a worldwide customer base of integrated device manufacturers, memory suppliers, fabless design houses, independent foundries, and R&D organizations. Its SEMulator3D modeling and analysis platform is used for fast and accurate ‘virtual fabrication’ of advanced manufacturing processes, allowing engineers to understand manufacturing effects early in the development process and reduce time-consuming and costly silicon learning cycles. Its MEMS design solutions are used to develop MEMS-based products for automotive, aerospace, industrial, defense, and consumer electronics applications, including smart phones, tablets, and gaming systems. The company is headquartered in Cary, North Carolina and has offices in California’s Silicon Valley, Waltham, Massachusetts, and Paris, France. More information is available at http://www.coventor.com.

    —end—

    Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw, supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.), imec China (IMEC Microelectronics Shanghai Co. Ltd.), imec India (Imec IMEC India
    Private Limited) and imec USA (IMEC Inc).

    Coventor and SEMulator3D are registered trademarks of Coventor, Inc. All other trademarks are the property of their respective owners.

  • Coventor’s CTO sounds off about foundry strategy, memory, process technology and lithography.

     

    Semiconductor Engineering sat down to discuss the foundry business, memory, process technology, lithography and other topics with David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. What follows are excerpts of that conversation.

    SE: Chipmakers are ramping up 16nm/14nm finFETs today, with 10nm and 7nm finFETs just around the corner. What do you see happening at these advanced nodes, particularly at 7nm?

    Fried: Most people are predicting evolutionary scaling from 14nm to 10nm to 7nm. It’s doubtful that we will see anything really earth-shattering in these technologies. And so, a lot of the challenges come down to patterning. We are going to see multi-patterning schemes really take hold at more levels. For example, the fins are now based on self-aligned double patterning. People will move into self-aligned quad patterning. The gates are maybe self-aligned double. Now, they will move into self-aligned quad. So, that’s going to be a big expense, because each level is going to have multiple passes and multiple cuts.

    SE: What are the challenges here?

    Fried: One of the big challenges is the multi-patterning piece. The second piece is that as you go through these evolutionary scaling points, there are a lot of other things that could break. We are trying to deposit very thin films in very high aspect ratio trenches. Again, with finer patterning, we will need incredibly low tolerances for etch. Atomic-level variability for both etch and deposition is going to get pressed to the limits in these technologies.

    SE: What else?

    Fried: There’s a crossover technology coming up here. What I mean by crossover is when is EUV? The challenge is that you will have to pick a technology and commit that technology to use EUV. This is long before you can really use it in the fab for development. That’s a tremendous challenge. 7nm might be a technology that the foundries are going to commit for EUV. But they will spend the next two or three years developing the technology without high-volume EUV tools.

    SE: Why is that an issue?

    Fried: Basically, you will need to have all of these multi-patterning schemes developed for the development wafers. Then, you must vet out a technology that may not even use them. You will have to figure out design rules and process validation ground rules on a technology that will be developed without the lithography manufacturing platform. There is a crossover out there somewhere. Maybe it’s 7nm. But essentially, you are putting a technology together on a lithography platform that doesn’t exist yet. That’s a big challenge here.

    SE: What does that mean for foundries and their customers?

    Fried: If you think about that challenge, you have to also think what that means economically. That, I believe, is why people are pushing customers towards 7nm rather than 10nm. The strategy is to develop the technology and the hard process aspects for 10nm. And then they take that, shrink it a little bit, and perhaps get EUV in at 7nm. The only thing they are figuring out at 7nm is the EUV piece. All of the other challenging processes are figured out at 10nm. What that also means is if it works, 7nm will be much cheaper to produce than 10nm.

    SE: Still, foundry customers must make some tough choices. For example, do they go from 16nm/14nm to 10nm? Or do they skip 10nm and jump to 7nm?

    Fried: It’s a time, cost and risk balance. Each customer will have to balance their cost and timeline risk very carefully to make that choice. Basically, 10nm is a significantly lower risk. It will happen on a relatively predictable time line. But it will have the understood density penalty of 10nm with a pervasive deployment of multi-patterning. And it will have the cost penalty, as far as we can tell, of not using EUV. 7nm starts to look like a real technology scaling node. It will start to drive cost down. If my predictions are right, they may try and squeeze 7nm into the high-volume manufacturing path of EUV.

    SE: TSMC and others might wait and insert EUV at 5nm, right?

    Fried: Clearly, TSMC is working on EUV. They don’t plan to deploy it for 7nm in high-volume. It may be deployed at 5nm. That may be one generation off in the crossover point. But the generation where they finally get EUV in, it starts to look like a real scaling node.

    SE: What about new technologies like nanowire FETs and III-V materials in the channels?

    Fried: I am looking for these earth-shattering breakthroughs. When do we get nanowires? When do you get alternative channel materials? I don’t see things happening fast enough on those groundbreaking options for it to happen at 7nm. I don’t foresee earth-shattering transistor elements in the next generation or two.

    SE: Any thoughts on the cadence of the nodes?

    Fried: Everybody, including Intel, is saying the technology nodes are stretching out. One day, these nodes might be three years apart instead of two. Maybe longer as we go further out.

    SE: Let’s focus on Lithography. Where is that heading?

    Fried: If you look around, there’s multi-patterning, EUV and DSA. A couple of years ago, EUV was supposedly coming. The patterning and integration community said that all we had to do was glue together this multi-patterning thing a little bit, because then EUV would save us. EUV has been pushed out long enough that multi-patterning has really grown some muscle. What I see is a lot more rigor, discipline and intensity on the multi-patterning front. The industry really understands the problems and is driving it to high-volume manufacturing by necessity. It has gone from a garage band to something professional over the last couple of years.

    SE: If EUV misses the 5nm window, the industry is talking about self-aligned octuple patterning (SAOP). Some say SAOP is impossible. Any comments?

    Fried: Two years ago, we said the same thing about SAQP. Then, we graduated from SADP to SAQP. What about SAOP? Today, it’s seems out of the question. But we are one multiplication away from SAOP.

    SE: What about EUV?

    Fried: EUV is making huge progress. For example, you have the pellicle, resist defectivity and other issues. Those things were dark clouds a few years ago. Now, the problems are clearly defined and there are competing solutions. People are working on them and those will be solved.

    SE: What about DSA?

    Fried: We are going to start to see more DSA, but not necessarily for conventional patterning. The first time we see DSA will be in pattern healing or pattern repair. Again, that will be an incremental improvement. It will be an evolutionary addition to the patterning scheme. It will not be a groundbreaking or earth-shattering change, especially in logic. We may see DSA for memory, because the designs are so much more regular. But we are still pretty far away from high-volume manufacturing applications for DSA.

    SE: Which lithographic technologies will be the ultimate winners and losers?

    Fried: Everyone wants to know which technology is going to win—multi-patterning, EUV or DSA. It’s been my view that all three of them are going to win. They may all live in the same technology and flow in the foundry.

    SE: Can you give us an example?

    Fried: By the time we get EUV inserted, for example, it might require EUV with SADP. It might also require SADP with DSA healing. It might be DSA in one layer and EUV in another layer.

    SE: The winning lithographic technology comes down to cost, right?

    Fried: Everything gets back to cost. One way to look at cost is through patterning fidelity. Then, there is process cost. This involves time and throughput.

    SE: Besides patterning, the back-end-of-the-line (BEOL) is another major challenge, right?

    Fried: The back-of-the-line is becoming limited. Nobody is scaling the low-k dielectric. Nobody has come up with another metallization scheme to replace copper. I don’t see groundbreaking changes in the backend. These are problems. In effect, we are squeezing the same technology for multiple generations.

    SE: Another issue is low-k dielectrics, right?

    Fried: Nobody has moved past a k-effective beyond about 2.4. People have played around with 2.2. But the reliability is really tricky down there. People are also working on new liners and things like that, but it’s really challenging to get the RC delay down in the backend. In fact, the RC delay is going up exponentially. That’s limiting overall product scaling significantly. Again, unless someone comes up with an alternative metallization scheme, or an alternative pitch layer, we’re in trouble in the backend as well.

    SE: Let’s switch gears. How do you see the 3D NAND market going?

    Fried: 3D NAND is an amazing innovation. By moving the bit-string into the third dimension, this technology eases many of the patterning-scaling challenges, at least for a generation or so.

    SE: What are the challenges with 3D NAND?

    Fried: It has introduced several fairly complex and new processes, such as a deep etch through a multi-layer stack. This etch is really complex. Uniformity is absolutely critical to the performance of the memory device. Billions of these holes are being etched on each die and across the entire 300mm wafer.

    SE: What else?

    Fried: Once the etch is complete, the amount of processing that takes place inside that hole is also pretty impressive. It rivals or even maybe exceeds the complexity of the DRAM stacked capacitor formation process. Again, uniformity of these processes is critical. So, from my perspective, much of the challenge here is focused on variability control of several key processes. This is either control from the process/equipment side, or integration techniques that make the flow robust/insensitive to variation.

    SE: Any thoughts on next-generation memories like MRAM, phase change or ReRAM?

    Fried: I would expect these advanced memories to first find homes in applications that recognize or leverage one of their unique advantages. This is long before we ever settle on one winner. I would also expect there to be several different technologies that win in the end, just as SRAM, DRAM and NAND have coexisted for generations.


 Products

  • SEMulator3D®
    SEMulator3D® is a powerful 3D semiconductor and MEMS process modeling platform that offers wide ranging technology development capabilities....

  • SEMulator3D® is a powerful 3D semiconductor and MEMS process modeling platform that offers wide ranging technology development capabilities. Based on highly efficient physics-driven voxel modeling technology, SEMulator3D has a unique ability to model complete process flows.

    Starting from input design data, SEMulator3D follows an integrated process flow description to create the virtual equivalent of the complex 3D structures created in the fab. Because the full integrated process sequence is modeled, SEMulator3D has the ability to predict downstream ramifications of process changes that would otherwise require build-and-test cycles in the fab.

  • CoventorWare
    CoventorWare is an integrated suite of design and simulation software that has the accuracy, capacity, and speed to address real-world MEMS designs....

  • CoventorWare is an integrated suite of design and simulation software that has the accuracy, capacity, and speed to address real-world MEMS designs. The suite has many MEMS-specific features for modeling and simulating a wide range of MEMS devices, including inertial sensors (accelerometers and gyros),microphonesresonators, and actuators. The included field solvers provide comprehensive coverage of MEMS-specific multi-physics, such as electrostatics, coupled electro-mechanics, piezoelectric, piezoresistive, and damping effects.

    mems simulation

    Simulated displacement due to fabrication-induced residual stress in mechanical layer of an accelerometer

    Whether exploring design concepts or performing detailed verification of device behavior, CoventorWare users leverage years of Coventor’s MEMS simulation experience and continuous improvement as well as the ever-increasing power of high-performance computers. Widely recognized within the MEMS industry as the best-in-class solution for multi-physics MEMS simulation, CoventorWare sets the standard for MEMS simulation accuracy, capacity and speed.


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MEMS, Semiconductor

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