LB Semicon

Pyeongtaek-si, Gyeonggi-do, 
Korea (South)
  • Booth: 5314

Welcome to LB Semicon, the best bumping solution provider:)

LB Semicon provides services such as bumping, probe testing and back-end services for the display driver IC, CMOS image sensor, and power management IC that are used in TVs, smartphones, and other electronic devices.

Since its establishment in February 2000, the company has actively worked together with top semiconductor producers at home and abroad and has accumulated mass production experience and knowhow, all of which has contributed to its even more advanced technology of today.

With its cutting-edge technology and spirit of enterprise, LB Semicon promises to serve as a company that provides products and services of the highest quality so that we can help promote the stature of Korea as a global semiconductor powerhouse and move forward alongside our customers.


    Wafer Level Chip Scale Package...

  • Wafer-level Packaging (WLCSP) is the technology of packaging and testing an integrated circuit while at the wafer level and then slicing it into chips to make the completed product, which differs from the conventional method of slicing the processed wafer first into individual chips and then packaging them. WLCSP is a true chip-scale packaging technology.

    Demand for WLCSP is increasing rapidly in the mobile market, due to the realization of a true chip-scale package with excellent electrical properties and price competitiveness. The WLCSP continues to expand its scope of application.

    LB Semicon currently provides various layers of WLCSP solutions ranging from two layers to six layers tailored to meet the needs of our customers.


    不同于以往的加工晶元后,一一切割芯片后,再进行封装的传统方式。晶圆级封装(Wafer Level Package) WLCSP将晶元进行封装和测试后,切割芯片,将完成品制作而成,是可实现芯片最小化的封装方法。WLCSP不仅可将芯片封装大小与芯片大小一致,还具备优秀的导电特性及较高的价格竞争力,得益于此,移动市场需求与日俱增,适用本技术的产品不断增多。如今,公司为满足客户需求,提供从2 layer至6 layer多样结构的WLCSP服务。

  • Au Bumping
    Gold Bumping...

  • Gold bumped wafers are in general applied on packages such as Tape Carrier Package (TCP), Chip on Glass (COG) and Chip on Film (COF), primarily for consumer products.

    This technology was developed as an alternative to the wire bonding technology. The gold bumped chip will be mounted on the package through the thermal compression method.

    As demand is increasing for thin and lightweight packages with high I/O and flexible interconnection, these gold bumped wafers will represent a suitable solution for such products as mobile devices.

    用金子凸块处理的晶元利用于安装在普通消费品的TCP(Tape Carrier Package), COG (Chip on Glass), COF(Chip on Film)封装。

    这一技术为了取代wire bond技术而诞生。用金子凸块的晶元通过热压缩完成贴附与封装表面。


  • Solder Bumping
    Solder Bumping...

  • A solder bump is being applied on various flip chip packages such as COC, fcBGA and fcQFN. LB Semicon currently provides a Lead-free solder bump solution based on a fine pitch structure, and even for the products such as wafers designed for QFN purpose that are not suitable for flip chip packages because of the pad position. Flip chip packages can still be applied without changing their pad layout with the help of the RDL process.

    Solder bump利用于 COC, fcBGA, fcQNF等多样的flip chip封装工序中。如今,LBSemicon支持fine pitch的Lead free solder bump工序。
    用于QFN的晶元和基板位置不适合flip chip封装的产品,通过RDL,不必改变基板格式,可实现flip chip封装。

  • Au RDL
    Au Redistribution...

  • Au RDL is mostly used to reposition the layout of the I/O pad so that the product becomes suitable for the wire bonding package. Au RDL provides an excellent wire bond-ability and high reliability, and it accomplishes SIP by repositioning the layout of the I/O pad in a way that makes it possible to apply a stack die wire bonding more easily without the pad layout design changes of memory devices.

    Au RDL一般用于重组 I/O基板格式,以便利用于wire bonding package。 Au RDL提供卓越的wire bond-ability和高信任度,利用Au RDL,无需改变存储终端基板的格式,通过重新布置基板位置,实现SIP,最终便捷轻松地完成stack die wire bonding。

  • Wafer Test
    Chip Probe Test...

  • A wafer test is a process where all the chips at wafer level are probed by testers dedicated to each IC to check whether a device’s functions and performance are consistent with the design specifications. In the process, general tests such as O/S and function checks are carried out to determine Pass/Fail results.

    In this process, only good dies are selected and defected ones are labeled, for example by leaving ink dots on the surface of their chips, thereby being sidelined in the subsequent assembly processes. All these processes employ auto wafer probers so that most of the processes are performed automatically.

    Wafer Test是利用各个IC专用测试仪对晶元上全部的芯片进行探测,确认终端的功能与设计规格是否一致,对O/S检查及功能是否正常进行全面检查,从而判断质量过关与否。

    在此过程中筛选出合格产品(Good die),在不合格产品表面上加以Ink Dotting标记,以便在后续工序中予以排除。 该工序利用自动晶圆探针
    (Auto Wafer Prober)进行,全程几乎自动完成。

  • Back-end Service
    Laminating - Back Grinding - Laser Marking - Foil Mount - Laser Grooving - Saw Dicing - UV Irradiation - Pick up & Place (Tray or T&R) - Visual Inspection - Packing...

  • Depending on our client’s feedback regarding products that have completed wafer testing, we provide a diverse selection of back-end services such as back grinding, laser marking, dicing saw, and visual inspection, as well as convenient drop ship services that encompass everything from packing (tray or tape & reel) processes to storage and delivery.

    针对完成晶圆检测的产品,根据客户的需求,我们不仅提供研磨、激光打标、切割、肉眼检查等多种后线服务,还提供包装(Tray or Tape&Reel)、保管、邮寄等直运服务。

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