JCET Group

As the electronics industry moves towards more complex semiconductor packages that are smaller, faster, and higher performance, engineers are faced with the challenge of trying to fit more powerful components into a smaller area without causing long-term reliability issues or stress on a package. Delivering the optimum package design requires an in-depth analysis of key package measurements and simulation.

JCET’s worldwide package characterization teams located in China, Singapore, South Korea, and the United States provide advanced package characterization services for our global customers to ensure they have high quality, high performance, reliable, and cost-effective package designs that meet their market requirements.

JCET offers a full suite of assembly services to meet our customers’ semiconductor packaging needs, including lead frame, laminate, flip chip interconnect, and advanced wafer-level technology.

JCET differentiates itself by providing a comprehensive platform of wafer-level technology that includes Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD), and Through Silicon Via (TSV) to meet the increasing market demand for next-generation devices with higher levels of integration, increased functionality, and compact sizes.

We collaborate with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time, and cost. Our comprehensive wafer-level technology platform provides customers with a wide range of choices for 2.5D and 3D package integration in advanced mobile devices such as smartphones and tablets.