JCET Group

JCET SiP solutions are enhanced by multiple advanced technologies including double-sided molding technology, EMI electromagnetic shielding technology, and laser-assisted bonding (LAB).

1. Double-sided molding: the technology effectively reduces the package size, shortens the connection of multiple dies and passive devices, reduces resistance, and improves the electrical performance of the system.
2. EMI shielding: JCET uses back metallization technology to effectively improve thermal conductivity and EMI shielding.
3. Laser-assisted bonding (LAB): the technology is able to overcome traditional reflow bonding problems, such as CTE mismatch, high warpage, high thermal mechanical stress, and other reliability problems.

Today’s consumers are looking for powerful, multi-functional electronic devices with unprecedented performance and speed, yet small, thin, and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device.  JCET is an industry leader in providing a comprehensive platform of wafer level technology solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD), Through Silicon Via (TSV), Encapsulated Chip Package (ECP), and Radio Frequency Identification (RFID).

JCET offers a wide range of wafer level technologies including embedded Wafer Level Ball Grid Array (eWLB), encapsulated Wafer Level Chip Scale Packages (eWLCSP), Wafer Level Chip Scale Packages (WLCSP), Integrated Passive Devices (IPD), Encapsulated Chip Package (ECP), and Radio Frequency Identification (RFID).

Flip Chip packaging, in which the silicon die is directly attached to the substrate using solder bumps instead of wirebonds, provides a dense interconnect with high electrical and thermal performance. Flip Chip interconnection provides the ultimate in miniaturization, reduced package parasitics and enables new paradigms in power and ground distribution to the chip not feasible in other traditional packaging approaches. 

JCET offers a broad Flip Chip portfolio--from large single die packages with passive components to modules and complex advanced 3D packaging, with a variety of low cost and innovative options. 

From our worldwide factories, JCET provides fully integrated test services and capabilities including:

•  Front-end test development services and test consultation services
•  Wafer test, including testing of bumped wafers and known good die (KGD) solutions for assembly of stacked die into a single package
•  Final test of simple and advanced packages using advanced test technology and automatic control of the test process that restricts yield losses to hard failures in the silicon itself
•  A full suite of optimized post-test services for rapid delivery of the final products to the end customer
•  Comprehensive system level test with the highest possible throughput and lowest cost of test

JCET combines operational efficiencies with its proven capabilities and competency to achieve the lowest cost of test (COT) with the highest possible throughput. By engaging JCET early in the product development process, customers benefit from JCET’s experience and guidance for a rapid, predictable, and problem-free production ramp.