he development of IC technology has significantly reduced the structural widths of silicon, which has increased the potential risk of interference.
The higher sensitivity to interference is caused by the lower supply voltages, higher switching speeds and lower switching thresholds of the ICs.
This also increases the sensitivity to ESD interference in particular.
Interference suppression and fault isolation are usually carried out with an ESD generator (ESD gun)
.
The ESD gun is a very coarse tool that exposes the assembly in a large area and does not allow the weak points to be located. It is almost impossible to locate the specific weak points quickly.
A lot of time is wasted on trial and error. For instance, if the tip of the ESD gun is placed on the left-hand metal component of the test object (LAN socket) and the gun head is swung downwards onto the test object, the processor will malfunction (display failure of the device under test).
The fault location cannot be narrowed down any further with the ESD gun. Now it is traditionally necessary to continue working by trial and error. Based on assumptions, various countermeasures are added and tested until success is achieved.
Solution with TroubleStar ESD / Burst
This practical example shows a new method for implementing this interference suppression more quickly. This requires new strategies and equipment technology.
The core component is the TroubleStar ESD / Burst (TS 23) with a pulse rise time of 1.5 ns and differential outputs.
How does the error occur?
Figure 1 shows the test device in the position with the ESD gun in which the fault occurs.
Working hypothesis
From the knowledge of how the ESD gun works and the structure of the test device, it is possible to guess that the SSD card or the processor may play a role in the fault scenario.
The tip of the ESD gun directs the interference pulse into a metallic component (LAN socket) of the device under test. As a side effect, this ESD gun generates a 200 ps steep E-field decoupling at the gun head, which also acts on the device under test.
It is unclear whether the device under test is disturbed by the ESD pulse from the tip (LAN socket) or by the parasitic effect of the E-field decoupling via the gun head. There are two places where interference suppression can be continued: at the network socket or at the point where the gun head acts.
Figure 1 shows that an SSD card is located in the immediate vicinity of the gun head. The electric field of the ESD gun head generates a current pulse that is coupled through the heat sink of the SSD card and capacitively to the circuit board of the SSD card and can therefore cause the SSD card to fail.
These and other hypotheses are tested with the TS 23 interference generator.

The first step is to check whether the microprocessor is sufficiently resistant to interference. A pulse current is sent once through the metal insert (A, B in Figure 2) of the microprocessor using the differential output of the TS 23 interference generator. This generates an ESD-like magnetic field in the processor underneath. Next, the interference voltage of the
TS 23 generator is applied between the metal insert and the ground (in Figure 2: B, C). There was no influence on the processor. This virtually eliminates any direct influence on the processor via its own heat sink.
It is suspected that the SSD card has a corresponding vulnerability.
A microprocessor with an oscillating quartz crystal is located on the SSD PCB directly under the SSD card heat sink. The SSD card is insulated from its heat sink. This allows an electric field to build up between the heat sink and the assembly (microprocessor, oscillating quartz crystal). A capacitive displacement current of the electric field couples into the conduction of the oscillating crystal. This current flows through the protective diode of the input of the oscillator circuit and raises the output voltage of the quartz crystal above the switching threshold of the oscillator input. The input no longer receives a crystal signal and the oscillator circuit no longer emits a clock signal for a few microseconds.
The microcontroller is no longer clocked for this time and stops. Communication with the processor is interrupted. The processor goes into an error state (display failure).
To prove this, a voltage is applied between the SSD heat sink and the SSD circuit board using the differential output of the TroubleStar ESD / Burst to generate an ESD-like field between the two (in Figure 2: D).
This measure led to the described failure of the test device. The error is caused by an interference voltage difference between the SSD heat sink and the SSD circuit board.
Furthermore, the connector of the SSD card to the electronics board is tested for interference immunity. The differential output of the TroubleStar ESD / Burst is connected to the electronic ground of the SSD PCB and the ground of the board (in Figure 2: E) in order to couple an ESD-like current via the connector.
In addition, other parts of the circuit can be examined using a magnetic field probe fed differentially by the TS 23 (in Figure 2: F), for example.
Countermeasures

n order to short-circuit the electrical field between the heat sink and the SSD circuit board, both metal systems must be electrically connected twice if possible, e.g. at points M2 and M3 (Figure 3).
To reduce the load on the PCB connector, the heat sink can also be connected to the ground of the electronics board M1 (Figure 3).
Countermeasures at M2 and M3 were successfull.