Silvaco

2811 Mission College Blvd.
Santa Clara,  CA  95054

United States
http://www.Silvaco.com
  • Booth: 2141

Silvaco, Inc. is a leading EDA and IP provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. New for DesignWest, Silvaco has added a large portfolio of hard design IP to its SIPware catalog for a premier foundry.
Silvaco delivers a full TCAD-to- sign-off flow for vertical markets including: displays, power electronics, optical devices, radiation and soft error reliability and advanced CMOS process and IP development. For over 30 years, Silvaco has enabled its customers to bring superior products to market with reduced cost and in the shortest time. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.


 Press Releases

  • Silvaco Announces Viola 10X – An Order of Magnitude Faster Characterization for Nanometer Silicon

    Timing and Power Characterization of Standard Cell Libraries, I/O Pads and Memories Accelerated by 10X through Intelligent Optimization Technology

    SANTA CLARA - May 28, 2019 - Silvaco Inc., a leading global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced Viola 10X, a scalable semiconductor intellectual property (IP) characterization and modeling tool which is the latest addition to the Silvaco Foundation IP product line.

    By leveraging new Intelligent Optimization delivering 10X faster performance and embedding Silvaco's SmartSpice simulator and Jivaro-A reduction technology, the fully automated Viola 10X flow delivers accurate modeling and characterization of standard cell libraries, input/output (I/O) pad circuitry and digital memories for designs targeted at nanometer process nodes.

    Viola 10X is an advanced characterization system that automatically performs static structural analysis on transistor-level netlists of standard cells and complex custom cells or macros. It uses the results of this analysis to set up complete characterization constraints and then leverages the foundry-certified, highly accurate and accelerated SmartSpice simulator to increase the overall throughput of timing, power, noise and statistical static timing analysis (SSTA) model generation. Viola 10X not only offers faster characterization capabilities, it supports all industry-standard model formats and includes a closed-loop model validation flow that allows users to seamlessly launch third-party tools to verify the generated models.

    “Certus provides the most advanced solutions for optimizing area, power, Electro-Static-Discharge (ESD) protection, features and performance of I/O circuits,” said Stephen Fairbanks, Director at Certus Semiconductor. “With Viola 10X, we met the tight development and characterization schedule for our client, a leading provider of IoT sensors. Its 10X-faster throughput makes no compromises in accuracy and enables optimization of the area, power, and performance of I/O pad circuitry.”

    “With Viola 10X developers no longer need in-depth knowledge of a circuit's electrical operation to properly set up a characterization run. Manual modeling efforts are eliminated which leads to reduced delay in model development and excludes human errors,” said Ole Christian Andersen, General Manager of the EDA Division at Silvaco. “The technology in Viola 10X extracts functionality, identifies all electrical arcs, and optimizes the complete characterization methodology for efficiency and accuracy, significantly reducing the time and effort to create models and delivers 10X faster characterization through the use of Silvaco’s Intelligent Optimization technology.”

    Viola 10X: Faster, More Reliable Model Sign-off

    At the heart of Viola 10X are Silvaco's proprietary circuit-function recognition, vector generation, SmartSpice simulation and Jivaro-A reduction technologies. Each contributes to the ease of setup, accelerated characterization throughput and quality of model sign-off in Silvaco's characterization solution:

    • Leveraging intelligent algorithms, Viola 10X automatically recognizes and models the functionality of standard cells and generates an efficient vector set for all timing arcs. By eliminating time-consuming, manual analyses, Viola 10X dramatically reduces the time required to set up and characterize I/O pads across a wide range of functional modes, process points, supply voltages and junction temperatures. The ability to efficiently handle the increasing number of process, voltage, temperature (PVT) points and operating modes is critical to nanometer design success.
    • The smart topology-driven vector generation of Viola 10X features unique structure-based vector optimization and an intrinsic, simulation-induced constraint acceleration algorithm. These features eliminate vector redundancy and avoid unnecessary simulation while maintaining characterization accuracy. Viola 10X also offers a flexible methodology, allowing the user to supply a vector set and its sequence for specific measurements.
    • Viola 10X supports commercially available SPICE simulators, including Silvaco's SmartSpice. When used in conjunction with SmartSpice, the optimized vector generation capabilities of Viola 10X deliver an order-of-magnitude faster throughput than previous generations of Viola, without any loss of accuracy. SmartSpice is a full SPICE simulator in wide use by analog/mixed-signal designers, foundries and IP developers down to 5nm.
    • Jivaro-A is the industry-leading RC parasitic reduction technology for layout parasitic extraction (LPE). Its circuit optimization is based on accuracy requirements, stability of simulation, realistic values, reliability of analysis and verifiability. Jivaro-A is not a simple data crunching or filtering tool. Optimized for SPICE netlists, it reduces simulation time, increases accuracy compared to built-in reduction of circuit simulators and offers blazing fast processing.

    Pricing and Availability 
    Viola 10X is available now. Contact Sales@Silvaco.com for more details.

    56th Design Automation Conference 
    Silvaco will showcase its suite of solutions from Atoms to Systems at the 56th Design Automation Conference (DAC) in Las Vegas, Nevada, June 3 – 5. Silvaco technology experts will be available to discuss and demonstrate our broad portfolio of smart solutions with emphasis on new products and capabilities such as Viola 10X.

    About Silvaco, Inc.

    Silvaco Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

    Press/Media Contact:
    press@silvaco.com

  • CEA-Leti and Silvaco Team Up on Yield-Prediction Project For Ultra-Low-Power Static Memories

    Project Combines CEA-Leti’s Semiconductor Development Expertise and Silvaco’s SPICE Simulation and Variability Analysis Technologies

    LetiLAS VEGAS – June 3, 2019 - Leti, a research institute of CEA-Tech, and Silvaco Inc., a leading global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced, during the 56th Design Automation Conference (DAC) in Las Vegas, a project to estimate and model the yield of ultra-low-voltage (ULV), ultra-low-leakage (ULL) static random access memory (SRAM) used in computing applications. Accurate yield prediction in the early stage of the IC design cycle lowers manufacturing costs and improves quality.

    Variability in manufacturing is highly detrimental to mass production yield of silicon chips with large memories, such as embedded caches. The Accelerated Simulation of Array for Yield Assessment (ASAYA) Project at CEA-Leti aims to validate the estimates based on electrical SPICE circuit simulations against silicon results after manufacturing. The challenge is to assess whether low failure rates (in the order of one failure in 1 billion) observed in simulation guarantee acceptable production yields for SRAMs above the MB range. In the past, such failures could be investigated successfully through classical Monte Carlo-based electrical simulation of bitcells, which allowed estimations with sufficient precision of the immunity margin against failures; or through the quasi-Monte Carlo method, which consists in evaluating the margin as a “number of sigmas,” assuming its distribution follows Gauss’s law. Recent (2018) publications still report these methods, showcasing that finer evaluations are difficult to work through, often using in-house software, which cannot be generalized to cover all required manufacturing process, voltage and temperature (PVT) conditions for the end-user device.

    The fail-detection and yield-estimation analysis at CEA-Leti will employ Silvaco’s VarMan eXtreme Memory Analysis (XMA) tool. The project will use extreme yield estimation (XYE) analysis to obtain failure rates and yield estimation at the full memory-circuit level, and extreme fail detection (XFD) analysis to investigate the PVT-dependent failure modes. VarMan employs machine-learning and flow-optimization methods to enable variability analysis of more than 6-sigma in a reasonable runtime.

    “Setting up advanced methods is essential with emerging technologies developed by CEA-Leti and the increase of memories’ needs. If a new method allows characterizing memory designs more quickly at a given condition of use, the entire characterization process that covers all conditions is accelerated,” said Emmanuel Sabonnadiere, CEO of CEA-Leti. “We therefore have a faster method to validate our memory with confidence that it will work within the expected failure rate, which will be compatible with the cost of production and market expectations.

    “For instance, the technological impact of the non-normality we have seen might lead to unexpected failures in all cases where the product operating conditions are pushed very close to the expected performance limits,” he said, “in particular for memories in Internet of Things products.”

    The research team is analyzing a 256 Kb ULV/ULL SRAM designed by CEA-Leti. Against current assumptions used in industry about yield and variability, evidence of non-Gaussian margin distribution in some cases has been found with the help of Silvaco VarMan. The project will feature measurements of silicon dies processed in the 28nm Ultra-Thin Fully Depleted Silicon on Insulator (UT-FDSOI) technology from STMicroelectronics to assess the predictive power of VarMan XMA.

    “Efficiently detecting failures and accurately estimating yield in SRAM and other kinds of memory arrays are fundamental to the development of reliable electronic devices,” said Firas Mohamed, VP/GM Machine Learning & Flow Optimization Division at Silvaco. “Shrinking silicon geometries and growing complexity are placing an even greater premium on fast statistical analysis to capture and evaluate all the variability effects found in nanometer-scale design. Building on past successes of CEA-Leti and Silvaco’s collaboration, this project will provide technologists with a powerful, high-accuracy predictive technology from Silvaco validated by CEA-Leti’s physical silicon production. We are gratified that CEA-Leti has chosen Silvaco and its trusted high-sigma-analysis technology for this project.”

    About CEA-Leti

    CEA-Leti, a technology research institute at CEA, is a global leader in miniaturization technologies enabling smart, energy-efficient and secure solutions for industry. Founded in 1967, Leti pioneers micro-& nanotechnologies, tailoring differentiating applicative solutions for global companies, SMEs and startups. Leti tackles critical challenges in healthcare, energy and digital migration. From sensors to data processing and computing solutions, Leti’s multidisciplinary teams deliver solid expertise, leveraging world-class pre-industrialization facilities. With a staff of more than 1,900, a portfolio of 2,700 patents, 91,500 sq. ft. of cleanroom space and a clear IP policy, the institute is based in Grenoble, France, and has offices in Silicon Valley and Tokyo. Leti has launched 60 startups and is a member of the Carnot Institutes network. Follow us on www.leti-cea.com and @CEA_Leti.

    CEA Tech is the technology research branch of the French Alternative Energies and Atomic Energy Commission (CEA), a key player in innovative R&D, defence & security, nuclear energy, technological research for industry and fundamental science, identified by Thomson Reuters as the second most innovative research organization in the world. CEA Tech leverages a unique innovation-driven culture and unrivalled expertise to develop and disseminate new technologies for industry, helping to create high-end products and provide a competitive edge.

    Press/Media Contact:
    Agency
    +33 6 74 93 23 47
    sldampoux@mahoneylyle.com

    About Silvaco, Inc.

    Silvaco Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

    Press/Media Contact:
    press@silvaco.com

  • Samsung Foundry Begins Partnership with Silvaco to Launch their Semiconductor IP Assets

    Santa Clara, CA - May 13, 2019 - Silvaco Inc., a leading supplier of EDA software and design IP, today announced that the semiconductor design IP of Samsung Foundry is now marketed, licensed and supported through Silvaco. Inc. The addition of Samsung production-proven design IP complements Silvaco’s existing SIPware™ IP products and solutions—embedded processors, wired interfaces, bus fabrics, peripheral controllers, cores for automotive, consumer and IoT/sensor applications. The initial offering of hard design IP is for the 14nm process node and is expected to extend to advanced technology nodes at 11nm, 10nm and 8nm, as well as mature planar technologies such as 28nm.

    “After identifying the requirements for different consumer, mobile, and HPC applications, we have compiled a full suite of design IPs which include wired and high-speed interfaces, analog and mixed-signal blocks and advanced security hard/soft cores,” said Jaehong Park, executive vice president of Design Platform Development Team at Samsung Electronics. “In partnership with Silvaco, we are bringing our proven IP to SoC engineers world-wide.”

    “Design IP is the fastest growing part of Silvaco’s business, and we saw a 50% sales growth in 2018,” said Babak Taheri, CTO and EVP of Products at Silvaco. “We expect accelerated growth with our Samsung Foundry partnership to deliver and support their proven IP to SoC design teams world-wide. Silvaco has an established track record, with multiple Tier 1 IP semiconductor companies, to unlock their assets and deliver their captive IP to the market. We are gratified that Silvaco is a trusted partner for the Samsung Foundry suite of advanced IP. We look forward to extending our partnership with this premier foundry for current and future technology nodes.”

    Availability 
    Samsung Foundry hard and soft design IP will be offered by Silvaco starting in June 2019. Contact IP@silvaco.com for more details.

    Samsung Foundry Forum 2019 
    At the fourth annual Samsung Foundry Forum, on May 14 in Santa Clara, Calif., Samsung Foundry and industry experts will share their latest innovations in process technology, packaging technology, IP and design solutions, and design services. Silvaco technologists will be available to discuss its SIPware™ IP products at the networking reception in the Samsung Partner Pavilion, 5:30-7:00 PM.

    About Silvaco, Inc.

    Silvaco Inc. is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan and Asia.

    Press/Media Contact:
    press@silvaco.com


 Products

  • Silvaco SIPWare Design IP
    Silvaco in partnership with Samsung Foundry is bringing its proven IP to SoC engineers worldwide. Targeting mobile, IoT, auto and AI applications, the suite includes wired and high-speed interfaces, analog and mixed-signal blocks and security cores....

  • On May 13, Silvaco announced the semiconductor design IP of Samsung Foundry is now marketed, licensed and supported through Silvaco. The addition of Samsung production-proven design IP complements Silvaco’s existing SIPware IP products and solutions—embedded processors, wired interfaces, bus fabrics, peripheral controllers, cores for automotive, consumer and IoT/sensor applications. The initial offering of hard design IP is for the 14nm process node and is expected to extend to advanced technology nodes at 11nm, 10nm and 8nm, as well as mature planar technologies such as 28nm.

    Silvaco has an established track record, with multiple Tier 1 IP semiconductor companies, to unlock their assets and deliver their captive IP to the market. Silvaco has taken the next step and became a trusted partner of Samsung Foundry.  Design IP is the fastest growing part of Silvaco’s business, and we expect accelerated growth with our Samsung Foundry partnership
  • Victory Atomistic
    Victory Atomistic, a TCAD modeling and simulation tool for atomic-level analysis of next generation semiconductor devices and materials....

  • Victory Atomistic extends Moore’s law through model creation and simulation of transistors and new memory technologies that approach the sub-nanometer scale.  For more than 20 years Silvaco has been a leading provider of TCAD solutions for semiconductor device and process simulation with world-wide adoption of its Victory™ TCAD tools by top semiconductor companies. Victory Atomistic is the first commercial realization of an atomistic nanoelectronics modeling and simulation tool.  The tool has been proven by Tier 1 semiconductor companies and is used as the golden-reference device simulator for investigation of advanced physics phenomena aimed at extending Moore’s law. Victory Atomistic is a powerful solution that enables creation and validation of advanced semiconductors before running silicon through manufacturing which ultimately saves time-to-market and hundreds of millions of dollars in development costs.

  • Viola 10X
    The fully automated Viola 10X flow delivers accurate modeling and characterization of standard cell libraries, input/output (I/O) pad circuitry and digital memories for designs targeted at nanometer process nodes...

  • Viola 10X is an advanced characterization system that automatically performs static structural analysis on transistor-level netlists of standard cells and complex custom cells. It uses the results of this analysis to set up complete characterization constraints and leverages the foundry-certified, highly accurate and accelerated SmartSpice simulator to increase the overall throughput of timing, power, noise and statistical static timing analysis (SSTA) model generation. Viola 10X supports all industry-standard model formats and includes a closed-loop model validation flow that seamlessly launches third-party tools to verify the generated models.

    Stephen Fairbanks, at Certus Semiconductor had the following experience: “With Viola 10X, we met the tight development and characterization schedule for our client, a leading provider of IoT sensors. Its 10X-faster throughput made no compromises in accuracy and enabled optimization of the PPA of I/O pad circuitry.”


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